URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [clk_and_reset.v] - Rev 31

Rev	Log message	Author	Age	Path
21	reg -> wire in and or mux in logic	unneback	5129d 05h	/versatile_library/trunk/rtl/verilog/clk_and_reset.v
18	naming convention vl_	unneback	5130d 16h	/versatile_library/trunk/rtl/verilog/clk_and_reset.v
17		unneback	5194d 06h	/versatile_library/trunk/rtl/verilog/clk_and_reset.v
4	added counters	unneback	5221d 11h	/versatile_library/trunk/rtl/verilog/clk_and_reset.v
3	various updates counter added	unneback	5224d 06h	/versatile_library/trunk/rtl/verilog/clk_and_reset.v