OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Rev 100

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
100 added cache mem with pipelined B4 behaviour unneback 4828d 15h /versatile_library/trunk/rtl/verilog/defines.v
98 work in progress unneback 4832d 14h /versatile_library/trunk/rtl/verilog/defines.v
97 cache is work in progress unneback 4834d 06h /versatile_library/trunk/rtl/verilog/defines.v
94 clock domain crossing unneback 4839d 07h /versatile_library/trunk/rtl/verilog/defines.v
92 wb b3 dpram with testcase unneback 4839d 15h /versatile_library/trunk/rtl/verilog/defines.v
83 new BE_RAM unneback 4842d 16h /versatile_library/trunk/rtl/verilog/defines.v
76 dependency for wb3 to avalon bus unneback 4846d 16h /versatile_library/trunk/rtl/verilog/defines.v
75 added wb to avalon bridge unneback 4846d 16h /versatile_library/trunk/rtl/verilog/defines.v
62 WB_B3_RAM_BE updates, bte port map + define dependency unneback 4893d 14h /versatile_library/trunk/rtl/verilog/defines.v
61 WB_B3_RAM_BE updates, bte port map + define dependency unneback 4893d 14h /versatile_library/trunk/rtl/verilog/defines.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 4895d 10h /versatile_library/trunk/rtl/verilog/defines.v
59 added WB RAM B3 with byte enable unneback 4896d 10h /versatile_library/trunk/rtl/verilog/defines.v
49 added WB_B4RAM with byte enable unneback 4927d 16h /versatile_library/trunk/rtl/verilog/defines.v
48 wb updated unneback 4934d 10h /versatile_library/trunk/rtl/verilog/defines.v
44 added target independet IO functionns unneback 5035d 09h /versatile_library/trunk/rtl/verilog/defines.v
43 added logic for parity generation and check unneback 5039d 12h /versatile_library/trunk/rtl/verilog/defines.v
42 updated mux_andor unneback 5043d 12h /versatile_library/trunk/rtl/verilog/defines.v
40 new build environment with custom.v added as a result file unneback 5043d 14h /versatile_library/trunk/rtl/verilog/defines.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.