URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Rev 72

Rev	Log message	Author	Age	Path
62	WB_B3_RAM_BE updates, bte port map + define dependency	unneback	4920d 20h	/versatile_library/trunk/rtl/verilog/defines.v
61	WB_B3_RAM_BE updates, bte port map + define dependency	unneback	4920d 20h	/versatile_library/trunk/rtl/verilog/defines.v
60	added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed	unneback	4922d 16h	/versatile_library/trunk/rtl/verilog/defines.v
59	added WB RAM B3 with byte enable	unneback	4923d 16h	/versatile_library/trunk/rtl/verilog/defines.v
49	added WB_B4RAM with byte enable	unneback	4954d 23h	/versatile_library/trunk/rtl/verilog/defines.v
48	wb updated	unneback	4961d 16h	/versatile_library/trunk/rtl/verilog/defines.v
44	added target independet IO functionns	unneback	5062d 15h	/versatile_library/trunk/rtl/verilog/defines.v
43	added logic for parity generation and check	unneback	5066d 18h	/versatile_library/trunk/rtl/verilog/defines.v
42	updated mux_andor	unneback	5070d 18h	/versatile_library/trunk/rtl/verilog/defines.v
40	new build environment with custom.v added as a result file	unneback	5070d 20h	/versatile_library/trunk/rtl/verilog/defines.v