URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Rev 52

Rev	Log message	Author	Age	Path
48	wb updated	unneback	4938d 08h	/versatile_library/trunk/rtl/verilog/memories.v
40	new build environment with custom.v added as a result file	unneback	5047d 11h	/versatile_library/trunk/rtl/verilog/memories.v
31	sync FIFO updated	unneback	5096d 08h	/versatile_library/trunk/rtl/verilog/memories.v
28	added sync simplex FIFO	unneback	5097d 09h	/versatile_library/trunk/rtl/verilog/memories.v
27	added sync simplex FIFO	unneback	5097d 09h	/versatile_library/trunk/rtl/verilog/memories.v
26	typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q	unneback	5097d 11h	/versatile_library/trunk/rtl/verilog/memories.v
25	added sync FIFO	unneback	5098d 00h	/versatile_library/trunk/rtl/verilog/memories.v
23	fixed port map error in async fifo 1r1w	unneback	5099d 22h	/versatile_library/trunk/rtl/verilog/memories.v
21	reg -> wire in and or mux in logic	unneback	5101d 00h	/versatile_library/trunk/rtl/verilog/memories.v
18	naming convention vl_	unneback	5102d 11h	/versatile_library/trunk/rtl/verilog/memories.v
14	reg -> wire for various signals	unneback	5172d 13h	/versatile_library/trunk/rtl/verilog/memories.v
11	async fifo simplex	unneback	5174d 02h	/versatile_library/trunk/rtl/verilog/memories.v
7	mem update	unneback	5176d 01h	/versatile_library/trunk/rtl/verilog/memories.v
5	memories added	unneback	5189d 02h	/versatile_library/trunk/rtl/verilog/memories.v