URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Rev 62

Rev	Log message	Author	Age	Path
60	added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed	unneback	4895d 08h	/versatile_library/trunk/rtl/verilog/memories.v
48	wb updated	unneback	4934d 09h	/versatile_library/trunk/rtl/verilog/memories.v
40	new build environment with custom.v added as a result file	unneback	5043d 13h	/versatile_library/trunk/rtl/verilog/memories.v
31	sync FIFO updated	unneback	5092d 09h	/versatile_library/trunk/rtl/verilog/memories.v
28	added sync simplex FIFO	unneback	5093d 11h	/versatile_library/trunk/rtl/verilog/memories.v
27	added sync simplex FIFO	unneback	5093d 11h	/versatile_library/trunk/rtl/verilog/memories.v
26	typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q	unneback	5093d 12h	/versatile_library/trunk/rtl/verilog/memories.v
25	added sync FIFO	unneback	5094d 02h	/versatile_library/trunk/rtl/verilog/memories.v
23	fixed port map error in async fifo 1r1w	unneback	5096d 00h	/versatile_library/trunk/rtl/verilog/memories.v
21	reg -> wire in and or mux in logic	unneback	5097d 01h	/versatile_library/trunk/rtl/verilog/memories.v
18	naming convention vl_	unneback	5098d 13h	/versatile_library/trunk/rtl/verilog/memories.v
14	reg -> wire for various signals	unneback	5168d 15h	/versatile_library/trunk/rtl/verilog/memories.v
11	async fifo simplex	unneback	5170d 03h	/versatile_library/trunk/rtl/verilog/memories.v
7	mem update	unneback	5172d 03h	/versatile_library/trunk/rtl/verilog/memories.v
5	memories added	unneback	5185d 04h	/versatile_library/trunk/rtl/verilog/memories.v