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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [registers.v] - Rev 107

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Rev Log message Author Age Path
100 added cache mem with pipelined B4 behaviour unneback 4900d 22h /versatile_library/trunk/rtl/verilog/registers.v
98 work in progress unneback 4904d 21h /versatile_library/trunk/rtl/verilog/registers.v
97 cache is work in progress unneback 4906d 12h /versatile_library/trunk/rtl/verilog/registers.v
94 clock domain crossing unneback 4911d 13h /versatile_library/trunk/rtl/verilog/registers.v
75 added wb to avalon bridge unneback 4918d 23h /versatile_library/trunk/rtl/verilog/registers.v
64 SPR reset value unneback 4965d 20h /versatile_library/trunk/rtl/verilog/registers.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 4967d 16h /versatile_library/trunk/rtl/verilog/registers.v
48 wb updated unneback 5006d 17h /versatile_library/trunk/rtl/verilog/registers.v
41 typo in registers.v unneback 5115d 20h /versatile_library/trunk/rtl/verilog/registers.v
40 new build environment with custom.v added as a result file unneback 5115d 20h /versatile_library/trunk/rtl/verilog/registers.v
29 updated counter for level1 and level2 function unneback 5164d 17h /versatile_library/trunk/rtl/verilog/registers.v
24 added vl_dff_ce_set unneback 5167d 17h /versatile_library/trunk/rtl/verilog/registers.v
18 naming convention vl_ unneback 5170d 20h /versatile_library/trunk/rtl/verilog/registers.v
17 unneback 5234d 10h /versatile_library/trunk/rtl/verilog/registers.v
15 added delay line unneback 5240d 17h /versatile_library/trunk/rtl/verilog/registers.v
10 added dff_ce_clear unneback 5244d 10h /versatile_library/trunk/rtl/verilog/registers.v
8 added dff_ce_clear unneback 5244d 10h /versatile_library/trunk/rtl/verilog/registers.v
5 memories added unneback 5257d 12h /versatile_library/trunk/rtl/verilog/registers.v
3 various updates
counter added		 unneback 5264d 11h /versatile_library/trunk/rtl/verilog/registers.v

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