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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [registers.v] - Rev 148

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139 unneback 5094d 12h /versatile_library/trunk/rtl/verilog/registers.v
116 syncronizer clock unneback 5161d 20h /versatile_library/trunk/rtl/verilog/registers.v
100 added cache mem with pipelined B4 behaviour unneback 5170d 21h /versatile_library/trunk/rtl/verilog/registers.v
98 work in progress unneback 5174d 20h /versatile_library/trunk/rtl/verilog/registers.v
97 cache is work in progress unneback 5176d 11h /versatile_library/trunk/rtl/verilog/registers.v
94 clock domain crossing unneback 5181d 13h /versatile_library/trunk/rtl/verilog/registers.v
75 added wb to avalon bridge unneback 5188d 22h /versatile_library/trunk/rtl/verilog/registers.v
64 SPR reset value unneback 5235d 20h /versatile_library/trunk/rtl/verilog/registers.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 5237d 15h /versatile_library/trunk/rtl/verilog/registers.v
48 wb updated unneback 5276d 16h /versatile_library/trunk/rtl/verilog/registers.v
41 typo in registers.v unneback 5385d 19h /versatile_library/trunk/rtl/verilog/registers.v
40 new build environment with custom.v added as a result file unneback 5385d 20h /versatile_library/trunk/rtl/verilog/registers.v
29 updated counter for level1 and level2 function unneback 5434d 17h /versatile_library/trunk/rtl/verilog/registers.v
24 added vl_dff_ce_set unneback 5437d 16h /versatile_library/trunk/rtl/verilog/registers.v
18 naming convention vl_ unneback 5440d 20h /versatile_library/trunk/rtl/verilog/registers.v
17 unneback 5504d 09h /versatile_library/trunk/rtl/verilog/registers.v
15 added delay line unneback 5510d 17h /versatile_library/trunk/rtl/verilog/registers.v
10 added dff_ce_clear unneback 5514d 09h /versatile_library/trunk/rtl/verilog/registers.v
8 added dff_ce_clear unneback 5514d 09h /versatile_library/trunk/rtl/verilog/registers.v
5 memories added unneback 5527d 11h /versatile_library/trunk/rtl/verilog/registers.v

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