URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [registers.v] - Rev 70

Rev	Log message	Author	Age	Path
64	SPR reset value	unneback	4893d 14h	/versatile_library/trunk/rtl/verilog/registers.v
60	added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed	unneback	4895d 10h	/versatile_library/trunk/rtl/verilog/registers.v
48	wb updated	unneback	4934d 11h	/versatile_library/trunk/rtl/verilog/registers.v
41	typo in registers.v	unneback	5043d 14h	/versatile_library/trunk/rtl/verilog/registers.v
40	new build environment with custom.v added as a result file	unneback	5043d 14h	/versatile_library/trunk/rtl/verilog/registers.v
29	updated counter for level1 and level2 function	unneback	5092d 11h	/versatile_library/trunk/rtl/verilog/registers.v
24	added vl_dff_ce_set	unneback	5095d 11h	/versatile_library/trunk/rtl/verilog/registers.v
18	naming convention vl_	unneback	5098d 14h	/versatile_library/trunk/rtl/verilog/registers.v
17		unneback	5162d 03h	/versatile_library/trunk/rtl/verilog/registers.v
15	added delay line	unneback	5168d 11h	/versatile_library/trunk/rtl/verilog/registers.v
10	added dff_ce_clear	unneback	5172d 04h	/versatile_library/trunk/rtl/verilog/registers.v
8	added dff_ce_clear	unneback	5172d 04h	/versatile_library/trunk/rtl/verilog/registers.v
5	memories added	unneback	5185d 05h	/versatile_library/trunk/rtl/verilog/registers.v
3	various updates counter added	unneback	5192d 04h	/versatile_library/trunk/rtl/verilog/registers.v