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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [registers.v] - Rev 98

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98 work in progress unneback 5054d 18h /versatile_library/trunk/rtl/verilog/registers.v
97 cache is work in progress unneback 5056d 10h /versatile_library/trunk/rtl/verilog/registers.v
94 clock domain crossing unneback 5061d 11h /versatile_library/trunk/rtl/verilog/registers.v
75 added wb to avalon bridge unneback 5068d 20h /versatile_library/trunk/rtl/verilog/registers.v
64 SPR reset value unneback 5115d 18h /versatile_library/trunk/rtl/verilog/registers.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 5117d 14h /versatile_library/trunk/rtl/verilog/registers.v
48 wb updated unneback 5156d 15h /versatile_library/trunk/rtl/verilog/registers.v
41 typo in registers.v unneback 5265d 18h /versatile_library/trunk/rtl/verilog/registers.v
40 new build environment with custom.v added as a result file unneback 5265d 18h /versatile_library/trunk/rtl/verilog/registers.v
29 updated counter for level1 and level2 function unneback 5314d 15h /versatile_library/trunk/rtl/verilog/registers.v
24 added vl_dff_ce_set unneback 5317d 15h /versatile_library/trunk/rtl/verilog/registers.v
18 naming convention vl_ unneback 5320d 18h /versatile_library/trunk/rtl/verilog/registers.v
17 unneback 5384d 07h /versatile_library/trunk/rtl/verilog/registers.v
15 added delay line unneback 5390d 15h /versatile_library/trunk/rtl/verilog/registers.v
10 added dff_ce_clear unneback 5394d 08h /versatile_library/trunk/rtl/verilog/registers.v
8 added dff_ce_clear unneback 5394d 08h /versatile_library/trunk/rtl/verilog/registers.v
5 memories added unneback 5407d 09h /versatile_library/trunk/rtl/verilog/registers.v
3 various updates
counter added		 unneback 5414d 08h /versatile_library/trunk/rtl/verilog/registers.v

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