URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Rev 23

Rev	Log message	Author	Age	Path
23	fixed port map error in async fifo 1r1w	unneback	5211d 13h	/versatile_library/trunk/rtl/verilog/versatile_library.v
22	added binary counters	unneback	5211d 19h	/versatile_library/trunk/rtl/verilog/versatile_library.v
21	reg -> wire in and or mux in logic	unneback	5212d 15h	/versatile_library/trunk/rtl/verilog/versatile_library.v
18	naming convention vl_	unneback	5214d 02h	/versatile_library/trunk/rtl/verilog/versatile_library.v
17		unneback	5277d 15h	/versatile_library/trunk/rtl/verilog/versatile_library.v
15	added delay line	unneback	5283d 23h	/versatile_library/trunk/rtl/verilog/versatile_library.v
14	reg -> wire for various signals	unneback	5284d 04h	/versatile_library/trunk/rtl/verilog/versatile_library.v
13	cosmetic update	unneback	5284d 06h	/versatile_library/trunk/rtl/verilog/versatile_library.v
12	added wishbone comliant modules	unneback	5285d 02h	/versatile_library/trunk/rtl/verilog/versatile_library.v
11	async fifo simplex	unneback	5285d 16h	/versatile_library/trunk/rtl/verilog/versatile_library.v
10	added dff_ce_clear	unneback	5287d 15h	/versatile_library/trunk/rtl/verilog/versatile_library.v
8	added dff_ce_clear	unneback	5287d 15h	/versatile_library/trunk/rtl/verilog/versatile_library.v
7	mem update	unneback	5287d 16h	/versatile_library/trunk/rtl/verilog/versatile_library.v
6	added library files	unneback	5300d 17h	/versatile_library/trunk/rtl/verilog/versatile_library.v