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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Rev 50

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50 added WB_B4RAM with byte enable unneback 4927d 22h /versatile_library/trunk/rtl/verilog/versatile_library.v
49 added WB_B4RAM with byte enable unneback 4927d 22h /versatile_library/trunk/rtl/verilog/versatile_library.v
48 wb updated unneback 4934d 16h /versatile_library/trunk/rtl/verilog/versatile_library.v
46 updated parity unneback 5030d 20h /versatile_library/trunk/rtl/verilog/versatile_library.v
45 updated timing in io models unneback 5032d 14h /versatile_library/trunk/rtl/verilog/versatile_library.v
44 added target independet IO functionns unneback 5035d 14h /versatile_library/trunk/rtl/verilog/versatile_library.v
43 added logic for parity generation and check unneback 5039d 17h /versatile_library/trunk/rtl/verilog/versatile_library.v
42 updated mux_andor unneback 5043d 17h /versatile_library/trunk/rtl/verilog/versatile_library.v
41 typo in registers.v unneback 5043d 19h /versatile_library/trunk/rtl/verilog/versatile_library.v
40 new build environment with custom.v added as a result file unneback 5043d 19h /versatile_library/trunk/rtl/verilog/versatile_library.v
39 added simple port prio based wb arbiter unneback 5044d 16h /versatile_library/trunk/rtl/verilog/versatile_library.v
38 updated andor mux unneback 5044d 16h /versatile_library/trunk/rtl/verilog/versatile_library.v
37 corrected polynom with length 20 unneback 5050d 12h /versatile_library/trunk/rtl/verilog/versatile_library.v
36 added generic andor_mux unneback 5051d 21h /versatile_library/trunk/rtl/verilog/versatile_library.v
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 5052d 08h /versatile_library/trunk/rtl/verilog/versatile_library.v
34 added vl_mux2_andor and vl_mux3_andor unneback 5052d 08h /versatile_library/trunk/rtl/verilog/versatile_library.v
33 updated wb3wb3_bridge unneback 5065d 10h /versatile_library/trunk/rtl/verilog/versatile_library.v
32 added vl_pll for ALTERA (cycloneIII) unneback 5072d 20h /versatile_library/trunk/rtl/verilog/versatile_library.v
31 sync FIFO updated unneback 5092d 16h /versatile_library/trunk/rtl/verilog/versatile_library.v
30 updated counter for level1 and level2 function unneback 5092d 16h /versatile_library/trunk/rtl/verilog/versatile_library.v

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