URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Rev 23

Rev	Log message	Author	Age	Path
23	fixed port map error in async fifo 1r1w	unneback	5011d 01h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
22	added binary counters	unneback	5011d 06h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
21	reg -> wire in and or mux in logic	unneback	5012d 02h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
18	naming convention vl_	unneback	5013d 13h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
17		unneback	5077d 02h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
15	added delay line	unneback	5083d 10h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
14	reg -> wire for various signals	unneback	5083d 15h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
13	cosmetic update	unneback	5083d 17h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
12	added wishbone comliant modules	unneback	5084d 13h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
11	async fifo simplex	unneback	5085d 04h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
10	added dff_ce_clear	unneback	5087d 03h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
8	added dff_ce_clear	unneback	5087d 03h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
7	mem update	unneback	5087d 04h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
6	added library files	unneback	5100d 04h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v