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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Rev 24

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Rev Log message Author Age Path
24 added vl_dff_ce_set unneback 5098d 22h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
23 fixed port map error in async fifo 1r1w unneback 5099d 13h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
22 added binary counters unneback 5099d 18h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
21 reg -> wire in and or mux in logic unneback 5100d 14h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
18 naming convention vl_ unneback 5102d 01h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
17 unneback 5165d 15h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
15 added delay line unneback 5171d 22h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
14 reg -> wire for various signals unneback 5172d 04h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
13 cosmetic update unneback 5172d 05h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
12 added wishbone comliant modules unneback 5173d 01h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
11 async fifo simplex unneback 5173d 16h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
10 added dff_ce_clear unneback 5175d 15h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
8 added dff_ce_clear unneback 5175d 15h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
7 mem update unneback 5175d 16h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
6 added library files unneback 5188d 16h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v

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