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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Rev 26

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Rev Log message Author Age Path
25 added sync FIFO unneback 4932d 02h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
24 added vl_dff_ce_set unneback 4933d 10h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
23 fixed port map error in async fifo 1r1w unneback 4934d 00h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
22 added binary counters unneback 4934d 06h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
21 reg -> wire in and or mux in logic unneback 4935d 02h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
18 naming convention vl_ unneback 4936d 13h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
17 unneback 5000d 02h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
15 added delay line unneback 5006d 10h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
14 reg -> wire for various signals unneback 5006d 15h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
13 cosmetic update unneback 5006d 17h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
12 added wishbone comliant modules unneback 5007d 13h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
11 async fifo simplex unneback 5008d 03h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
10 added dff_ce_clear unneback 5010d 02h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
8 added dff_ce_clear unneback 5010d 02h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
7 mem update unneback 5010d 03h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
6 added library files unneback 5023d 04h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v

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