URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 22

Rev	Log message	Author	Age	Path
22	added binary counters	unneback	5183d 18h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
21	reg -> wire in and or mux in logic	unneback	5184d 14h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
18	naming convention vl_	unneback	5186d 01h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
17		unneback	5249d 14h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
15	added delay line	unneback	5255d 22h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
14	reg -> wire for various signals	unneback	5256d 03h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
13	cosmetic update	unneback	5256d 05h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
12	added wishbone comliant modules	unneback	5257d 01h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
11	async fifo simplex	unneback	5257d 16h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
10	added dff_ce_clear	unneback	5259d 15h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
8	added dff_ce_clear	unneback	5259d 15h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
7	mem update	unneback	5259d 16h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
6	added library files	unneback	5272d 16h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v