OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 29

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
29 updated counter for level1 and level2 function unneback 4937d 01h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
28 added sync simplex FIFO unneback 4938d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
27 added sync simplex FIFO unneback 4938d 02h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
25 added sync FIFO unneback 4938d 17h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
24 added vl_dff_ce_set unneback 4940d 01h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
23 fixed port map error in async fifo 1r1w unneback 4940d 16h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
22 added binary counters unneback 4940d 21h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
21 reg -> wire in and or mux in logic unneback 4941d 17h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
18 naming convention vl_ unneback 4943d 04h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
17 unneback 5006d 17h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
15 added delay line unneback 5013d 01h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
14 reg -> wire for various signals unneback 5013d 06h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
13 cosmetic update unneback 5013d 08h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
12 added wishbone comliant modules unneback 5014d 04h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
11 async fifo simplex unneback 5014d 19h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
10 added dff_ce_clear unneback 5016d 18h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
8 added dff_ce_clear unneback 5016d 18h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
7 mem update unneback 5016d 19h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v
6 added library files unneback 5029d 19h /versatile_library/trunk/rtl/verilog/versatile_library_altera.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.