URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [tags/] [Rev1/] [bench/] [Makefile] - Rev 92

Rev	Log message	Author	Age	Path
89		unneback	5107d 06h	/versatile_mem_ctrl/tags/Rev1/bench/Makefile
18	Updated the rtl/verilog Makefile and the bench Makefile.	mikaeljf	5286d 07h	/versatile_mem_ctrl/trunk/bench/Makefile
11	Initial version with support for DDR	mikaeljf	5391d 00h	/versatile_mem_ctrl/trunk/bench/Makefile
9	testbench	unneback	5418d 08h	/versatile_mem_ctrl/trunk/bench/Makefile