URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [tags/] [Rev1/] [bench/] [tb_defines.v] - Rev 92

Rev	Log message	Author	Age	Path
89		unneback	5107d 06h	/versatile_mem_ctrl/tags/Rev1/bench/tb_defines.v
74	Minor update of rtl Makefile.	mikaeljf	5223d 06h	/versatile_mem_ctrl/trunk/bench/tb_defines.v
33	work for limited test case, no cke inhibit for fifo empty	unneback	5248d 08h	/versatile_mem_ctrl/trunk/bench/tb_defines.v
17	Modified rtl Makefile and tb_defines.v	mikaeljf	5289d 06h	/versatile_mem_ctrl/trunk/bench/tb_defines.v
15	Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera.	mikaeljf	5290d 06h	/versatile_mem_ctrl/trunk/bench/tb_defines.v
11	Initial version with support for DDR	mikaeljf	5391d 00h	/versatile_mem_ctrl/trunk/bench/tb_defines.v