URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [tags/] [Rev1/] [bench/] [wb4_ddr.fzm] - Rev 92

Rev	Log message	Author	Age	Path
89		unneback	5084d 04h	/versatile_mem_ctrl/tags/Rev1/bench/wb4_ddr.fzm
75		mikaeljf	5196d 05h	/versatile_mem_ctrl/trunk/bench/wb4_ddr.fzm
69		mikaeljf	5204d 09h	/versatile_mem_ctrl/trunk/bench/wb4_ddr.fzm
15	Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera.	mikaeljf	5267d 04h	/versatile_mem_ctrl/trunk/bench/wb4_ddr.fzm
11	Initial version with support for DDR	mikaeljf	5367d 22h	/versatile_mem_ctrl/trunk/bench/wb4_ddr.fzm