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[/] [versatile_mem_ctrl/] [tags/] [Rev2/] [rtl/] [verilog/] [sdr_16_defines.v] - Rev 109

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Rev Log message Author Age Path
109 Rev2 from trunk unneback 4817d 10h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/sdr_16_defines.v
104 versatile_mem modules naming unneback 4998d 09h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/sdr_16_defines.v
95 new files unneback 5168d 04h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/sdr_16_defines.v
79 Added defines that fix bugs with slow wishbone clocks doing burst writes julius 5284d 02h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/sdr_16_defines.v
78 Burst writing working again, although its mostly hardcoded to burst 4. Also added a fix for when the RAM and bus clocks are about the same speed, to avoid buffer overrun julius 5286d 09h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/sdr_16_defines.v
76 Changed SDR16 synthesis useioff location, fsm_wb acking logic, default SDR build is for 16m part now julius 5299d 08h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/sdr_16_defines.v
64 Changed sdr 16 FSM to use defines instead of parameters which were somehow screwing up synplify, reinstated used of sdr_16_defines.v file julius 5310d 04h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/sdr_16_defines.v
62 Added note to sdr_16_defines.v asking if it's still used julius 5310d 14h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/sdr_16_defines.v
33 work for limited test case, no cke inhibit for fifo empty unneback 5328d 11h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/sdr_16_defines.v
5 pass initial testing unneback 5594d 08h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/sdr_16_defines.v
4 unneback 5595d 11h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/sdr_16_defines.v
3 unneback 5595d 13h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/sdr_16_defines.v

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