URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [bench/] [tb_defines.v] - Rev 17

Rev	Log message	Author	Age	Path
17	Modified rtl Makefile and tb_defines.v	mikaeljf	5412d 20h	/versatile_mem_ctrl/trunk/bench/tb_defines.v
15	Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera.	mikaeljf	5413d 21h	/versatile_mem_ctrl/trunk/bench/tb_defines.v
11	Initial version with support for DDR	mikaeljf	5514d 14h	/versatile_mem_ctrl/trunk/bench/tb_defines.v