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[/] [versatile_mem_ctrl/] [trunk/] [bench/] [tb_defines.v] - Rev 25

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17 Modified rtl Makefile and tb_defines.v mikaeljf 5423d 11h /versatile_mem_ctrl/trunk/bench/tb_defines.v
15 Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera. mikaeljf 5424d 11h /versatile_mem_ctrl/trunk/bench/tb_defines.v
11 Initial version with support for DDR mikaeljf 5525d 05h /versatile_mem_ctrl/trunk/bench/tb_defines.v

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