URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [rtl/] [verilog/] [Makefile] - Rev 11

Rev	Log message	Author	Age	Path
11	Initial version with support for DDR	mikaeljf	5367d 06h	/versatile_mem_ctrl/trunk/rtl/verilog/Makefile
6		unneback	5490d 11h	/versatile_mem_ctrl/trunk/rtl/verilog/Makefile
5	pass initial testing	unneback	5490d 11h	/versatile_mem_ctrl/trunk/rtl/verilog/Makefile
4		unneback	5491d 14h	/versatile_mem_ctrl/trunk/rtl/verilog/Makefile
3		unneback	5491d 17h	/versatile_mem_ctrl/trunk/rtl/verilog/Makefile
2	initial	unneback	5497d 15h	/versatile_mem_ctrl/trunk/rtl/verilog/Makefile