URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [rtl/] [verilog/] [Makefile] - Rev 14

Rev	Log message	Author	Age	Path
13	Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback.	mikaeljf	5389d 06h	/versatile_mem_ctrl/trunk/rtl/verilog/Makefile
11	Initial version with support for DDR	mikaeljf	5399d 18h	/versatile_mem_ctrl/trunk/rtl/verilog/Makefile
6		unneback	5522d 23h	/versatile_mem_ctrl/trunk/rtl/verilog/Makefile
5	pass initial testing	unneback	5522d 23h	/versatile_mem_ctrl/trunk/rtl/verilog/Makefile
4		unneback	5524d 02h	/versatile_mem_ctrl/trunk/rtl/verilog/Makefile
3		unneback	5524d 05h	/versatile_mem_ctrl/trunk/rtl/verilog/Makefile
2	initial	unneback	5530d 03h	/versatile_mem_ctrl/trunk/rtl/verilog/Makefile