URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [rtl/] [verilog/] [Makefile] - Rev 16

Rev	Log message	Author	Age	Path
15	Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera.	mikaeljf	5289d 06h	/versatile_mem_ctrl/trunk/rtl/verilog/Makefile
13	Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback.	mikaeljf	5379d 11h	/versatile_mem_ctrl/trunk/rtl/verilog/Makefile
11	Initial version with support for DDR	mikaeljf	5390d 00h	/versatile_mem_ctrl/trunk/rtl/verilog/Makefile
6		unneback	5513d 04h	/versatile_mem_ctrl/trunk/rtl/verilog/Makefile
5	pass initial testing	unneback	5513d 05h	/versatile_mem_ctrl/trunk/rtl/verilog/Makefile
4		unneback	5514d 08h	/versatile_mem_ctrl/trunk/rtl/verilog/Makefile
3		unneback	5514d 10h	/versatile_mem_ctrl/trunk/rtl/verilog/Makefile
2	initial	unneback	5520d 08h	/versatile_mem_ctrl/trunk/rtl/verilog/Makefile