| Rev |
Log message |
Author |
Age |
Path |
| 60 |
Added synthesis directives ensuring registering of right signals in IOBs for sdr16 controller. Removed comment stripping from vppreproc command for sdr_16 creation. |
julius |
5466d 07h |
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile |
| 50 |
Fixed up make file - THIS MAY BREAK THINGS, but it's a lot neater and easier to use, also dependencies are now properly configured, and we don't remake things unecessarily |
julius |
5473d 01h |
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile |
| 49 |
Added versatile_fifo_dual_port_ram_dc_sw.v rule to makefile, getting it from versatile fifo project |
julius |
5473d 02h |
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile |
| 42 |
added pipeline stage for egress FIFO readot |
unneback |
5475d 19h |
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile |
| 39 |
updated FIFO and SDR 16 |
unneback |
5476d 21h |
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile |
| 37 |
|
unneback |
5479d 19h |
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile |
| 35 |
work for limited test case |
unneback |
5480d 03h |
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile |
| 33 |
work for limited test case, no cke inhibit for fifo empty |
unneback |
5480d 06h |
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile |
| 31 |
Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. |
mikaeljf |
5485d 03h |
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile |
| 28 |
Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'. |
mikaeljf |
5489d 05h |
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile |
| 25 |
|
unneback |
5494d 22h |
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile |
| 24 |
Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions. |
mikaeljf |
5495d 09h |
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile |
| 22 |
Updated the Altera timing constraints file, also minor updates of defines file and Makefile. |
mikaeljf |
5504d 22h |
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile |
| 18 |
Updated the rtl/verilog Makefile and the bench Makefile. |
mikaeljf |
5518d 04h |
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile |
| 17 |
Modified rtl Makefile and tb_defines.v |
mikaeljf |
5521d 03h |
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile |
| 15 |
Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera. |
mikaeljf |
5522d 04h |
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile |
| 13 |
Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback. |
mikaeljf |
5612d 09h |
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile |
| 11 |
Initial version with support for DDR |
mikaeljf |
5622d 21h |
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile |
| 6 |
|
unneback |
5746d 02h |
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile |
| 5 |
pass initial testing |
unneback |
5746d 02h |
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile |
