URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [sim/] [rtl_sim/] [bin/] [sim_xilinx.tcl] - Rev 31

Rev	Log message	Author	Age	Path
31	Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts.	mikaeljf	5464d 03h	/versatile_mem_ctrl/trunk/sim/rtl_sim/bin/sim_xilinx.tcl
15	Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera.	mikaeljf	5501d 04h	/versatile_mem_ctrl/trunk/sim/rtl_sim/bin/sim_xilinx.tcl