URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [syn/] [altera/] [bin/] [versatile_memory_controller.sdc] - Rev 102

Rev	Log message	Author	Age	Path
86		mikaeljf	5294d 07h	/versatile_mem_ctrl/trunk/syn/altera/bin/versatile_memory_controller.sdc
84		mikaeljf	5299d 06h	/versatile_mem_ctrl/trunk/syn/altera/bin/versatile_memory_controller.sdc
83		mikaeljf	5300d 01h	/versatile_mem_ctrl/trunk/syn/altera/bin/versatile_memory_controller.sdc
81		mikaeljf	5301d 02h	/versatile_mem_ctrl/trunk/syn/altera/bin/versatile_memory_controller.sdc
30	Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts.	mikaeljf	5387d 23h	/versatile_mem_ctrl/trunk/syn/altera/bin/versatile_memory_controller.sdc
22	Updated the Altera timing constraints file, also minor updates of defines file and Makefile.	mikaeljf	5407d 18h	/versatile_mem_ctrl/trunk/syn/altera/bin/versatile_memory_controller.sdc
21	Updated the Altera timing constraints file (.sdc).	mikaeljf	5411d 22h	/versatile_mem_ctrl/trunk/syn/altera/bin/versatile_memory_controller.sdc
20	Minor update of sdc-file.	mikaeljf	5413d 23h	/versatile_mem_ctrl/trunk/syn/altera/bin/versatile_memory_controller.sdc
15	Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera.	mikaeljf	5425d 00h	/versatile_mem_ctrl/trunk/syn/altera/bin/versatile_memory_controller.sdc