URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [syn/] [xilinx/] [bin/] [versatile_memory_controller.ucf] - Rev 67

Rev	Log message	Author	Age	Path
19	Added do-file for Modelsim waveform viewer.	mikaeljf	5420d 06h	/versatile_mem_ctrl/trunk/syn/xilinx/bin/versatile_memory_controller.ucf
15	Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera.	mikaeljf	5425d 03h	/versatile_mem_ctrl/trunk/syn/xilinx/bin/versatile_memory_controller.ucf