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Subversion Repositories vga_lcd

[/] [vga_lcd/] [tags/] [rel_1/] [rtl/] [verilog/] [ud_cnt.v] - Rev 62

Rev	Log message	Author	Age	Path
62	New directory structure.	root	5665d 10h	/vga_lcd/tags/rel_1/rtl/verilog/ud_cnt.v
42	This commit was manufactured by cvs2svn to create tag 'rel_1'.		8181d 09h	/vga_lcd/tags/rel_1/rtl/verilog/ud_cnt.v
28	Changed counter-library. Changed vga-core. Added 32bpp mode.	rherveille	8263d 17h	/vga_lcd/tags/rel_1/rtl/verilog/ud_cnt.v
23	Added Copyright/Licence header	rherveille	8338d 09h	/vga_lcd/tags/rel_1/rtl/verilog/ud_cnt.v
17	Major rework. Included generic memory models. Core now supports pixel clocks at same speed as wishbone clock (except for 8bpp color mode)	rherveille	8396d 09h	/vga_lcd/tags/rel_1/rtl/verilog/ud_cnt.v
16	- Changed Directory Structure - Added verilog Source Code - Changed IO pin names and defines statements	rudi	8423d 15h	/vga_lcd/tags/rel_1/rtl/verilog/ud_cnt.v