URL https://opencores.org/ocsvn/vga_lcd/vga_lcd/trunk

Subversion Repositories vga_lcd

[/] [vga_lcd/] [tags/] [rel_1/] [rtl/] [verilog/] [vga_tgen.v] - Rev 62

Rev	Log message	Author	Age	Path
62	New directory structure.	root	5624d 14h	/vga_lcd/tags/rel_1/rtl/verilog/vga_tgen.v
42	This commit was manufactured by cvs2svn to create tag 'rel_1'.		8140d 13h	/vga_lcd/tags/rel_1/rtl/verilog/vga_tgen.v
28	Changed counter-library. Changed vga-core. Added 32bpp mode.	rherveille	8222d 21h	/vga_lcd/tags/rel_1/rtl/verilog/vga_tgen.v
23	Added Copyright/Licence header	rherveille	8297d 13h	/vga_lcd/tags/rel_1/rtl/verilog/vga_tgen.v
17	Major rework. Included generic memory models. Core now supports pixel clocks at same speed as wishbone clock (except for 8bpp color mode)	rherveille	8355d 13h	/vga_lcd/tags/rel_1/rtl/verilog/vga_tgen.v
16	- Changed Directory Structure - Added verilog Source Code - Changed IO pin names and defines statements	rudi	8382d 19h	/vga_lcd/tags/rel_1/rtl/verilog/vga_tgen.v