URL https://opencores.org/ocsvn/vga_lcd/vga_lcd/trunk

Subversion Repositories vga_lcd

[/] [vga_lcd/] [tags/] [rel_19/] [bench/] [verilog/] [sync_check.v] - Rev 62

Rev	Log message	Author	Age	Path
62	New directory structure.	root	5599d 17h	/vga_lcd/tags/rel_19/bench/verilog/sync_check.v
61	This commit was manufactured by cvs2svn to create tag 'rel_19'.		7594d 14h	/vga_lcd/tags/rel_19/bench/verilog/sync_check.v
60	all WB outputs are registered, but just when we dont use cursors	markom	7594d 14h	/vga_lcd/tags/rel_19/bench/verilog/sync_check.v
52	Numerous updates and added checks	rherveille	7733d 17h	/vga_lcd/tags/rel_19/bench/verilog/sync_check.v
44	Changed timing section in VGA core, changed testbench accordingly. Fixed bug in 'timing check' test.	rherveille	7782d 15h	/vga_lcd/tags/rel_19/bench/verilog/sync_check.v
24	Updated testbench for VGA/LCD Core version 2.0	rherveille	8271d 20h	/vga_lcd/tags/rel_19/bench/verilog/sync_check.v
16	- Changed Directory Structure - Added verilog Source Code - Changed IO pin names and defines statements	rudi	8357d 21h	/vga_lcd/tags/rel_19/bench/verilog/sync_check.v