URL https://opencores.org/ocsvn/vga_lcd/vga_lcd/trunk

Subversion Repositories vga_lcd

[/] [vga_lcd/] [tags/] [rel_19/] [bench/] [verilog/] [tests.v] - Rev 62

Rev	Log message	Author	Age	Path
62	New directory structure.	root	5589d 04h	/vga_lcd/tags/rel_19/bench/verilog/tests.v
61	This commit was manufactured by cvs2svn to create tag 'rel_19'.		7584d 02h	/vga_lcd/tags/rel_19/bench/verilog/tests.v
60	all WB outputs are registered, but just when we dont use cursors	markom	7584d 02h	/vga_lcd/tags/rel_19/bench/verilog/tests.v
59	Removed ctrl register's clut and vide bank switch from the register test. As they get reset automatically. This may result to erroneous errors.	rherveille	7616d 07h	/vga_lcd/tags/rel_19/bench/verilog/tests.v
54	Added DVI tests	rherveille	7723d 00h	/vga_lcd/tags/rel_19/bench/verilog/tests.v
52	Numerous updates and added checks	rherveille	7723d 05h	/vga_lcd/tags/rel_19/bench/verilog/tests.v
44	Changed timing section in VGA core, changed testbench accordingly. Fixed bug in 'timing check' test.	rherveille	7772d 02h	/vga_lcd/tags/rel_19/bench/verilog/tests.v
38	Changed testbench to reflect modified VGA timing generator.	rherveille	8105d 05h	/vga_lcd/tags/rel_19/bench/verilog/tests.v
29	Added wb_ack delay section to testbench	rherveille	8177d 09h	/vga_lcd/tags/rel_19/bench/verilog/tests.v
26	Added 32bpp tests	rherveille	8187d 11h	/vga_lcd/tags/rel_19/bench/verilog/tests.v
24	Updated testbench for VGA/LCD Core version 2.0	rherveille	8261d 08h	/vga_lcd/tags/rel_19/bench/verilog/tests.v
16	- Changed Directory Structure - Added verilog Source Code - Changed IO pin names and defines statements	rudi	8347d 09h	/vga_lcd/tags/rel_19/bench/verilog/tests.v