URL https://opencores.org/ocsvn/vga_lcd/vga_lcd/trunk

Subversion Repositories vga_lcd

[/] [vga_lcd/] [trunk/] [bench/] [verilog/] [tests.v] - Rev 62

Rev	Log message	Author	Age	Path
62	New directory structure.	root	5590d 07h	/vga_lcd/trunk/bench/verilog/tests.v
60	all WB outputs are registered, but just when we dont use cursors	markom	7585d 04h	/vga_lcd/trunk/bench/verilog/tests.v
59	Removed ctrl register's clut and vide bank switch from the register test. As they get reset automatically. This may result to erroneous errors.	rherveille	7617d 10h	/vga_lcd/trunk/bench/verilog/tests.v
54	Added DVI tests	rherveille	7724d 03h	/vga_lcd/trunk/bench/verilog/tests.v
52	Numerous updates and added checks	rherveille	7724d 08h	/vga_lcd/trunk/bench/verilog/tests.v
44	Changed timing section in VGA core, changed testbench accordingly. Fixed bug in 'timing check' test.	rherveille	7773d 05h	/vga_lcd/trunk/bench/verilog/tests.v
38	Changed testbench to reflect modified VGA timing generator.	rherveille	8106d 07h	/vga_lcd/trunk/bench/verilog/tests.v
29	Added wb_ack delay section to testbench	rherveille	8178d 12h	/vga_lcd/trunk/bench/verilog/tests.v
26	Added 32bpp tests	rherveille	8188d 14h	/vga_lcd/trunk/bench/verilog/tests.v
24	Updated testbench for VGA/LCD Core version 2.0	rherveille	8262d 10h	/vga_lcd/trunk/bench/verilog/tests.v
16	- Changed Directory Structure - Added verilog Source Code - Changed IO pin names and defines statements	rudi	8348d 12h	/vga_lcd/trunk/bench/verilog/tests.v