URL https://opencores.org/ocsvn/vga_lcd/vga_lcd/trunk

Subversion Repositories vga_lcd

[/] [vga_lcd/] [trunk/] [rtl/] [verilog/] [generic_dpram.v] - Rev 62

Rev	Log message	Author	Age	Path
62	New directory structure.	root	5732d 00h	/vga_lcd/trunk/rtl/verilog/generic_dpram.v
43	Added WISHBONE revB.3 Registered Feedback Cycles support	rherveille	7915d 13h	/vga_lcd/trunk/rtl/verilog/generic_dpram.v
19	Major revisions throughout the core. Moved Color Lookup Table inside core. Changed control & status register contents. Changed port names to be conform to new naming convention. Fixed bug in CAB assertion. Changed video memory address generation. and many more ....	rherveille	8434d 01h	/vga_lcd/trunk/rtl/verilog/generic_dpram.v
17	Major rework. Included generic memory models. Core now supports pixel clocks at same speed as wishbone clock (except for 8bpp color mode)	rherveille	8462d 23h	/vga_lcd/trunk/rtl/verilog/generic_dpram.v