OpenCores
URL https://opencores.org/ocsvn/vga_lcd/vga_lcd/trunk

Subversion Repositories vga_lcd

[/] [vga_lcd/] [trunk/] [rtl/] [verilog/] [vga_defines.v] - Rev 62

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
62 New directory structure. root 5628d 13h /vga_lcd/trunk/rtl/verilog/vga_defines.v
57 1) Rewrote vga_fifo_dc. It now uses gray codes and a more elaborate anti-metastability scheme.
2) Changed top level and pixel generator to reflect changes in the fifo.
3) Changed a bug in vga_fifo.
4) Changed pixel generator and wishbone master to reflect changes.		 rherveille 7676d 11h /vga_lcd/trunk/rtl/verilog/vga_defines.v
53 Fixed some Wishbone RevB.3 related bugs.
Changed layout of the core. Blocks are located more logically now.
Started work on a dual clocked/double edge 12bit output. Commonly used by external devices like DVI transmitters.		 rherveille 7762d 13h /vga_lcd/trunk/rtl/verilog/vga_defines.v
30 Fixed some bugs discovered by modified testbench
Removed / Changed some strange logic constructions
Started work on hardware cursor support (not finished yet)
Changed top-level name to vga_enh_top.v		 rherveille 8216d 17h /vga_lcd/trunk/rtl/verilog/vga_defines.v
28 Changed counter-library.
Changed vga-core.
Added 32bpp mode.		 rherveille 8226d 19h /vga_lcd/trunk/rtl/verilog/vga_defines.v
23 Added Copyright/Licence header rherveille 8301d 11h /vga_lcd/trunk/rtl/verilog/vga_defines.v
19 Major revisions throughout the core.
Moved Color Lookup Table inside core.
Changed control & status register contents.
Changed port names to be conform to new naming convention.
Fixed bug in CAB assertion.
Changed video memory address generation.
and many more ....		 rherveille 8330d 14h /vga_lcd/trunk/rtl/verilog/vga_defines.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.