URL https://opencores.org/ocsvn/vga_lcd/vga_lcd/trunk

Subversion Repositories vga_lcd

[/] [vga_lcd/] [trunk/] [rtl/] [verilog/] [vga_enh_top.v] - Rev 62

Rev	Log message	Author	Age	Path
62	New directory structure.	root	5732d 00h	/vga_lcd/trunk/rtl/verilog/vga_enh_top.v
57	1) Rewrote vga_fifo_dc. It now uses gray codes and a more elaborate anti-metastability scheme. 2) Changed top level and pixel generator to reflect changes in the fifo. 3) Changed a bug in vga_fifo. 4) Changed pixel generator and wishbone master to reflect changes.	rherveille	7779d 23h	/vga_lcd/trunk/rtl/verilog/vga_enh_top.v
56	Removed 'or negedge arst' from sluint/luint sensitivity list	rherveille	7808d 19h	/vga_lcd/trunk/rtl/verilog/vga_enh_top.v
53	Fixed some Wishbone RevB.3 related bugs. Changed layout of the core. Blocks are located more logically now. Started work on a dual clocked/double edge 12bit output. Commonly used by external devices like DVI transmitters.	rherveille	7866d 01h	/vga_lcd/trunk/rtl/verilog/vga_enh_top.v
43	Added WISHBONE revB.3 Registered Feedback Cycles support	rherveille	7915d 13h	/vga_lcd/trunk/rtl/verilog/vga_enh_top.v
33	Added 64x64pixels 4bpp hardware cursor support.	rherveille	8294d 23h	/vga_lcd/trunk/rtl/verilog/vga_enh_top.v
30	Fixed some bugs discovered by modified testbench Removed / Changed some strange logic constructions Started work on hardware cursor support (not finished yet) Changed top-level name to vga_enh_top.v	rherveille	8320d 05h	/vga_lcd/trunk/rtl/verilog/vga_enh_top.v