URL https://opencores.org/ocsvn/vga_lcd/vga_lcd/trunk

Subversion Repositories vga_lcd

[/] [vga_lcd/] [trunk/] [rtl/] [verilog/] [vga_fifo_dc.v] - Rev 62

Rev	Log message	Author	Age	Path
62	New directory structure.	root	5738d 23h	/vga_lcd/trunk/rtl/verilog/vga_fifo_dc.v
57	1) Rewrote vga_fifo_dc. It now uses gray codes and a more elaborate anti-metastability scheme. 2) Changed top level and pixel generator to reflect changes in the fifo. 3) Changed a bug in vga_fifo. 4) Changed pixel generator and wishbone master to reflect changes.	rherveille	7786d 22h	/vga_lcd/trunk/rtl/verilog/vga_fifo_dc.v
53	Fixed some Wishbone RevB.3 related bugs. Changed layout of the core. Blocks are located more logically now. Started work on a dual clocked/double edge 12bit output. Commonly used by external devices like DVI transmitters.	rherveille	7873d 00h	/vga_lcd/trunk/rtl/verilog/vga_fifo_dc.v
28	Changed counter-library. Changed vga-core. Added 32bpp mode.	rherveille	8337d 06h	/vga_lcd/trunk/rtl/verilog/vga_fifo_dc.v
23	Added Copyright/Licence header	rherveille	8411d 22h	/vga_lcd/trunk/rtl/verilog/vga_fifo_dc.v
17	Major rework. Included generic memory models. Core now supports pixel clocks at same speed as wishbone clock (except for 8bpp color mode)	rherveille	8469d 21h	/vga_lcd/trunk/rtl/verilog/vga_fifo_dc.v
16	- Changed Directory Structure - Added verilog Source Code - Changed IO pin names and defines statements	rudi	8497d 04h	/vga_lcd/trunk/rtl/verilog/vga_fifo_dc.v