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[/] [w11/] [tags/] [w11a_V0.7/] [rtl/] [bplib/] [nexys2/] [nexys2_pins.ucf] - Rev 36

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Rev Log message Author Age Path
33 - major release w11a_V0.70 (tagged) wfjm 3295d 21h /w11/tags/w11a_V0.7/rtl/bplib/nexys2/nexys2_pins.ucf
17 - interim release w11a_V0.56 (untagged)
- re-organized handling of board and derived clocks in test benches
- added message filter definitions for some designs (.mfset files)
- added Cypress EZ-USB FX2 controller (USB interface)
- added firmware for EZ-USB FX2 supporting jtag access and data transfer
- FPGA configure over USB now supported directly in make build flow
- added test systems for USB testing and rlink over USB verification
- no functional change of w11a CPU core or any pre-existing test systems
- Note: Carefully read the disclaimer about usage of USB VID/PID numbers
in the file README_USB-VID-PID.txt. You'll be responsible for any
misuse of the defaults provided with the project sources !!		 wfjm 4195d 16h /w11/tags/w11a_V0.7/rtl/bplib/nexys2/nexys2_pins.ucf
15 - interim release w11a_V0.54 (untagged)
- add Nexys3 port of w11a		 wfjm 4590d 15h /w11/tags/w11a_V0.7/rtl/bplib/nexys2/nexys2_pins.ucf
12 - interim release w11a_V0.531 (untagged)
- many small changes to prepare upcoming support for Spartan-6 and
usage of Cypress FX2 USB interface on nexys2/3 and atlys boards		 wfjm 4673d 16h /w11/tags/w11a_V0.7/rtl/bplib/nexys2/nexys2_pins.ucf
8 - interim release w11a_V0.51 (untagged)
- migrate to ibus protocol verion 2
- nexys2 systems now with DCM derived system clock supported
- sys_w11a_n2 now runs with 58 MHz clksys		 wfjm 4962d 13h /w11/tags/w11a_V0.7/rtl/bplib/nexys2/nexys2_pins.ucf
2 initial source upload (no docs yet) wfjm 5103d 19h /w11/tags/w11a_V0.7/rtl/bplib/nexys2/nexys2_pins.ucf

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