Rev |
Log message |
Author |
Age |
Path |
38 |
Tag final OpenCores release w11a_V0.74 |
wfjm |
2824d 17h |
/w11/tags/w11a_V0.74/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd |
36 |
- Code base cleaned-up for vivado, fsm now inferred
- xsim support complete (but many issues to be resolved yet)
- Added configurable w11a cache
- Removed some never documented and now strategically obsolete designs |
wfjm |
2992d 19h |
/w11/tags/w11a_V0.74/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd |
35 |
- Add Arty support (BRAM only)
- Add sysmon/xadc support (for nexys4,basys3,arty designs)
- Add Vivado simulator support (DPI not yet working) |
wfjm |
3091d 19h |
/w11/tags/w11a_V0.74/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd |
30 |
- added RH70/RP/RM big disk support
- many cleanups |
wfjm |
3401d 18h |
/w11/tags/w11a_V0.74/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd |
27 |
- migrate to rlink protocol version 4
- Goals for rlink v4
- 16 bit addresses (instead of 8 bit)
- more robust encoding, support for error recovery at transport level
- add features to reduce round trips
- improved attention handling
- new 'list abort' command
- For further details see README_Rlink_V4.txt
- use own C++ based tcl shell tclshcpp instead of tclsh |
wfjm |
3546d 18h |
/w11/tags/w11a_V0.74/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd |
19 |
- interim release w11a_V0.562 (untagged)
- C++ and Tcl based backend server: many support classes for interfacing to
w11 system designs, and the associated Tcl bindings.
- add 'asm-11', a simple, Macro-11 syntax subset combatible, assembler.
- use now doxygen 1.8.3.1, generate c++,tcl, and vhdl source docs |
wfjm |
4162d 17h |
/w11/tags/w11a_V0.74/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd |
17 |
- interim release w11a_V0.56 (untagged)
- re-organized handling of board and derived clocks in test benches
- added message filter definitions for some designs (.mfset files)
- added Cypress EZ-USB FX2 controller (USB interface)
- added firmware for EZ-USB FX2 supporting jtag access and data transfer
- FPGA configure over USB now supported directly in make build flow
- added test systems for USB testing and rlink over USB verification
- no functional change of w11a CPU core or any pre-existing test systems
- Note: Carefully read the disclaimer about usage of USB VID/PID numbers
in the file README_USB-VID-PID.txt. You'll be responsible for any
misuse of the defaults provided with the project sources !! |
wfjm |
4263d 14h |
/w11/tags/w11a_V0.74/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd |
16 |
- interim release w11a_V0.55 (untagged)
- added xon/xoff (software flow control) support to serport library
- added test systems for serport verification
- use new serport stack in sys_w11a_* and sys_tst_rlink_* systems |
wfjm |
4640d 00h |
/w11/tags/w11a_V0.74/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd |
15 |
- interim release w11a_V0.54 (untagged)
- add Nexys3 port of w11a |
wfjm |
4658d 13h |
/w11/tags/w11a_V0.74/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd |
13 |
- interim release w11a_V0.532 (untagged)
- re-organize modules 'human I/O' interface on Digilent boards
- add test designs for 'human I/O' interface for atlys,nexys2, and s3board
- small updates in crc8 and dcm areas
- with one exception all vhdl sources use now numeric_std |
wfjm |
4672d 22h |
/w11/tags/w11a_V0.74/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd |
12 |
- interim release w11a_V0.531 (untagged)
- many small changes to prepare upcoming support for Spartan-6 and
usage of Cypress FX2 USB interface on nexys2/3 and atlys boards |
wfjm |
4741d 14h |
/w11/tags/w11a_V0.74/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd |
10 |
- add sources for C++/Tcl based backend, add directories
- tools/src/...
- tools/tcl/...
- tools/dox
- tools/make
- add rlink test system
- rtl/sys_gen/tst_rlink/nexys2/... |
wfjm |
4904d 23h |
/w11/tags/w11a_V0.74/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd |