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[/] [wbddr3/] [trunk/] [bench/] [cpp/] [ddrsdram_tb.cpp] - Rev 16

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16 New, modified code, now works in simulation!! dgisselq 3022d 22h /wbddr3/trunk/bench/cpp/ddrsdram_tb.cpp
14 Lots of changes. Redesigned the refresh logic, and the activate/precharge
logic. While it's still not working on the hardware, it looks better than
before. (I also caught some bugs in the MRx register settings ...)		 dgisselq 3038d 19h /wbddr3/trunk/bench/cpp/ddrsdram_tb.cpp
13 Cleanup, bug fixes--sadly, the code no longer works, so while it's "better"
in that it can build at 200MHz, it no longer works in the Verilator simulation.		 dgisselq 3039d 18h /wbddr3/trunk/bench/cpp/ddrsdram_tb.cpp
12 Added the write-read and write-precharge extra delays into both module and
simulation.		 dgisselq 3040d 22h /wbddr3/trunk/bench/cpp/ddrsdram_tb.cpp
10 This might just work ... at least, it passes my testbench. dgisselq 3041d 00h /wbddr3/trunk/bench/cpp/ddrsdram_tb.cpp
9 Making progress: The singular write and pipe read tests work. Random pipe
reads still failing.		 dgisselq 3041d 00h /wbddr3/trunk/bench/cpp/ddrsdram_tb.cpp
8 Singular reads and writes now work (in the Verilator simulator)--just not
pipelined reads or writes.		 dgisselq 3041d 09h /wbddr3/trunk/bench/cpp/ddrsdram_tb.cpp
7 Make lots of progress. Reset works, and refresh is within a clock measurement
or two of working properly. Singular sequential writes work as well.		 dgisselq 3042d 18h /wbddr3/trunk/bench/cpp/ddrsdram_tb.cpp
6 Lots of bug fixes. The controller now proceeds through the proper reset
logic into the first write. This includes activating the needed bank and the
next one, and then issuing the write command. It doesn't complete the write
command yet, but that's the next step.		 dgisselq 3043d 18h /wbddr3/trunk/bench/cpp/ddrsdram_tb.cpp
4 Work continues. A preliminary test-bench has been created. The core
has yet to pass through the reset cycle yet, so there's a lot of work
still to be done.		 dgisselq 3044d 16h /wbddr3/trunk/bench/cpp/ddrsdram_tb.cpp

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