URL https://opencores.org/ocsvn/wbddr3/wbddr3/trunk

Subversion Repositories wbddr3

[/] [wbddr3/] [trunk/] [bench/] [cpp/] [ddrsdramsim.cpp] - Rev 6

Rev	Log message	Author	Age	Path
6	Lots of bug fixes. The controller now proceeds through the proper reset logic into the first write. This includes activating the needed bank and the next one, and then issuing the write command. It doesn't complete the write command yet, but that's the next step.	dgisselq	3040d 03h	/wbddr3/trunk/bench/cpp/ddrsdramsim.cpp
5	Under Verilator/simulation testing, the core now properly brings the device up from reset. Next step: opening/closing banks.	dgisselq	3040d 09h	/wbddr3/trunk/bench/cpp/ddrsdramsim.cpp
4	Work continues. A preliminary test-bench has been created. The core has yet to pass through the reset cycle yet, so there's a lot of work still to be done.	dgisselq	3041d 01h	/wbddr3/trunk/bench/cpp/ddrsdramsim.cpp