URL https://opencores.org/ocsvn/wbddr3/wbddr3/trunk

Subversion Repositories wbddr3

[/] [wbddr3/] [trunk/] [bench/] [cpp/] [ddrsdramsim.cpp] - Rev 9

Rev	Log message	Author	Age	Path
9	Making progress: The singular write and pipe read tests work. Random pipe reads still failing.	dgisselq	3037d 07h	/wbddr3/trunk/bench/cpp/ddrsdramsim.cpp
8	Singular reads and writes now work (in the Verilator simulator)--just not pipelined reads or writes.	dgisselq	3037d 16h	/wbddr3/trunk/bench/cpp/ddrsdramsim.cpp
7	Make lots of progress. Reset works, and refresh is within a clock measurement or two of working properly. Singular sequential writes work as well.	dgisselq	3039d 01h	/wbddr3/trunk/bench/cpp/ddrsdramsim.cpp
6	Lots of bug fixes. The controller now proceeds through the proper reset logic into the first write. This includes activating the needed bank and the next one, and then issuing the write command. It doesn't complete the write command yet, but that's the next step.	dgisselq	3040d 01h	/wbddr3/trunk/bench/cpp/ddrsdramsim.cpp
5	Under Verilator/simulation testing, the core now properly brings the device up from reset. Next step: opening/closing banks.	dgisselq	3040d 07h	/wbddr3/trunk/bench/cpp/ddrsdramsim.cpp
4	Work continues. A preliminary test-bench has been created. The core has yet to pass through the reset cycle yet, so there's a lot of work still to be done.	dgisselq	3040d 23h	/wbddr3/trunk/bench/cpp/ddrsdramsim.cpp