URL https://opencores.org/ocsvn/wbddr3/wbddr3/trunk

Subversion Repositories wbddr3

[/] [wbddr3/] [trunk/] [bench/] [cpp/] [ddrsdramsim.h] - Rev 14

Rev	Log message	Author	Age	Path
14	Lots of changes. Redesigned the refresh logic, and the activate/precharge logic. While it's still not working on the hardware, it looks better than before. (I also caught some bugs in the MRx register settings ...)	dgisselq	3038d 22h	/wbddr3/trunk/bench/cpp/ddrsdramsim.h
13	Cleanup, bug fixes--sadly, the code no longer works, so while it's "better" in that it can build at 200MHz, it no longer works in the Verilator simulation.	dgisselq	3039d 21h	/wbddr3/trunk/bench/cpp/ddrsdramsim.h
12	Added the write-read and write-precharge extra delays into both module and simulation.	dgisselq	3041d 01h	/wbddr3/trunk/bench/cpp/ddrsdramsim.h
6	Lots of bug fixes. The controller now proceeds through the proper reset logic into the first write. This includes activating the needed bank and the next one, and then issuing the write command. It doesn't complete the write command yet, but that's the next step.	dgisselq	3043d 21h	/wbddr3/trunk/bench/cpp/ddrsdramsim.h
4	Work continues. A preliminary test-bench has been created. The core has yet to pass through the reset cycle yet, so there's a lot of work still to be done.	dgisselq	3044d 20h	/wbddr3/trunk/bench/cpp/ddrsdramsim.h