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[/] [wbddr3/] [trunk/] [bench/] [cpp/] [ddrsdramsim.h] - Rev 18

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18 We now pass all tests again--this time for a 4:1 controller, with a CAS of 5
and a CWL of 5. This is designed for a memory running at 320MHz,
transmitting across the data lines as 640Mbps, and yet running internally at
only 80MHz.		 dgisselq 2854d 18h /wbddr3/trunk/bench/cpp/ddrsdramsim.h
16 New, modified code, now works in simulation!! dgisselq 2882d 23h /wbddr3/trunk/bench/cpp/ddrsdramsim.h
14 Lots of changes. Redesigned the refresh logic, and the activate/precharge
logic. While it's still not working on the hardware, it looks better than
before. (I also caught some bugs in the MRx register settings ...)		 dgisselq 2898d 20h /wbddr3/trunk/bench/cpp/ddrsdramsim.h
13 Cleanup, bug fixes--sadly, the code no longer works, so while it's "better"
in that it can build at 200MHz, it no longer works in the Verilator simulation.		 dgisselq 2899d 19h /wbddr3/trunk/bench/cpp/ddrsdramsim.h
12 Added the write-read and write-precharge extra delays into both module and
simulation.		 dgisselq 2900d 23h /wbddr3/trunk/bench/cpp/ddrsdramsim.h
6 Lots of bug fixes. The controller now proceeds through the proper reset
logic into the first write. This includes activating the needed bank and the
next one, and then issuing the write command. It doesn't complete the write
command yet, but that's the next step.		 dgisselq 2903d 19h /wbddr3/trunk/bench/cpp/ddrsdramsim.h
4 Work continues. A preliminary test-bench has been created. The core
has yet to pass through the reset cycle yet, so there's a lot of work
still to be done.		 dgisselq 2904d 18h /wbddr3/trunk/bench/cpp/ddrsdramsim.h

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