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[/] [wbddr3/] [trunk/] [rtl/] [wbddrsdram.v] - Rev 12

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12 Added the write-read and write-precharge extra delays into both module and
simulation.		 dgisselq 3040d 23h /wbddr3/trunk/rtl/wbddrsdram.v
11 Fixed the bugs Xilinx's tools pointed out. dgisselq 3041d 00h /wbddr3/trunk/rtl/wbddrsdram.v
10 This might just work ... at least, it passes my testbench. dgisselq 3041d 01h /wbddr3/trunk/rtl/wbddrsdram.v
9 Making progress: The singular write and pipe read tests work. Random pipe
reads still failing.		 dgisselq 3041d 01h /wbddr3/trunk/rtl/wbddrsdram.v
8 Singular reads and writes now work (in the Verilator simulator)--just not
pipelined reads or writes.		 dgisselq 3041d 10h /wbddr3/trunk/rtl/wbddrsdram.v
7 Make lots of progress. Reset works, and refresh is within a clock measurement
or two of working properly. Singular sequential writes work as well.		 dgisselq 3042d 19h /wbddr3/trunk/rtl/wbddrsdram.v
6 Lots of bug fixes. The controller now proceeds through the proper reset
logic into the first write. This includes activating the needed bank and the
next one, and then issuing the write command. It doesn't complete the write
command yet, but that's the next step.		 dgisselq 3043d 19h /wbddr3/trunk/rtl/wbddrsdram.v
5 Under Verilator/simulation testing, the core now properly brings the device
up from reset. Next step: opening/closing banks.		 dgisselq 3044d 02h /wbddr3/trunk/rtl/wbddrsdram.v
4 Work continues. A preliminary test-bench has been created. The core
has yet to pass through the reset cycle yet, so there's a lot of work
still to be done.		 dgisselq 3044d 17h /wbddr3/trunk/rtl/wbddrsdram.v
3 Fixes some, not all, of the Verilator build/lint errors. dgisselq 3045d 09h /wbddr3/trunk/rtl/wbddrsdram.v
2 Initial checkin. Pieces are not working yet, but the general approach is
starting to take shape.		 dgisselq 3045d 10h /wbddr3/trunk/rtl/wbddrsdram.v

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