URL https://opencores.org/ocsvn/wbddr3/wbddr3/trunk

Subversion Repositories wbddr3

[/] [wbddr3/] [trunk/] [rtl/] [wbddrsdram.v] - Rev 5

Rev	Log message	Author	Age	Path
5	Under Verilator/simulation testing, the core now properly brings the device up from reset. Next step: opening/closing banks.	dgisselq	3019d 23h	/wbddr3/trunk/rtl/wbddrsdram.v
4	Work continues. A preliminary test-bench has been created. The core has yet to pass through the reset cycle yet, so there's a lot of work still to be done.	dgisselq	3020d 15h	/wbddr3/trunk/rtl/wbddrsdram.v
3	Fixes some, not all, of the Verilator build/lint errors.	dgisselq	3021d 07h	/wbddr3/trunk/rtl/wbddrsdram.v
2	Initial checkin. Pieces are not working yet, but the general approach is starting to take shape.	dgisselq	3021d 08h	/wbddr3/trunk/rtl/wbddrsdram.v