URL https://opencores.org/ocsvn/wbddr3/wbddr3/trunk

Subversion Repositories wbddr3

[/] [wbddr3/] [trunk/] [rtl/] [wbddrsdram.v] - Rev 7

Rev	Log message	Author	Age	Path
7	Make lots of progress. Reset works, and refresh is within a clock measurement or two of working properly. Singular sequential writes work as well.	dgisselq	3042d 20h	/wbddr3/trunk/rtl/wbddrsdram.v
6	Lots of bug fixes. The controller now proceeds through the proper reset logic into the first write. This includes activating the needed bank and the next one, and then issuing the write command. It doesn't complete the write command yet, but that's the next step.	dgisselq	3043d 19h	/wbddr3/trunk/rtl/wbddrsdram.v
5	Under Verilator/simulation testing, the core now properly brings the device up from reset. Next step: opening/closing banks.	dgisselq	3044d 02h	/wbddr3/trunk/rtl/wbddrsdram.v
4	Work continues. A preliminary test-bench has been created. The core has yet to pass through the reset cycle yet, so there's a lot of work still to be done.	dgisselq	3044d 18h	/wbddr3/trunk/rtl/wbddrsdram.v
3	Fixes some, not all, of the Verilator build/lint errors.	dgisselq	3045d 09h	/wbddr3/trunk/rtl/wbddrsdram.v
2	Initial checkin. Pieces are not working yet, but the general approach is starting to take shape.	dgisselq	3045d 11h	/wbddr3/trunk/rtl/wbddrsdram.v