URL https://opencores.org/ocsvn/wbuart32/wbuart32/trunk

Subversion Repositories wbuart32

[/] [wbuart32/] [trunk/] [bench/] [verilog/] [linetest.v] - Rev 13

Rev	Log message	Author	Age	Path
13	Adjusted documentation of OPT_STANDALONE, and updated internal README files.	dgisselq	2818d 11h	/wbuart32/trunk/bench/verilog/linetest.v
10	Adjusted for the new hardware flow control capability.	dgisselq	2818d 11h	/wbuart32/trunk/bench/verilog/linetest.v
5	Created independent peripheral, several toplevel tests, and updated documentation to match.	dgisselq	2863d 03h	/wbuart32/trunk/bench/verilog/linetest.v
2	A first version to be checked in. The rxuart.v and txuart.v files have been well tested elsewhere, although the test setup here has not been as well tested. Still, type 'make test' in the base directory and you will get an assurance that the entire thing works--if you would like.	dgisselq	2996d 12h	/wbuart32/trunk/bench/verilog/linetest.v