URL https://opencores.org/ocsvn/wbuart32/wbuart32/trunk

Subversion Repositories wbuart32

[/] [wbuart32/] [trunk/] [bench/] [verilog/] [linetest.v] - Rev 18

Rev	Log message	Author	Age	Path
18	Lots of updates. See the git log for details	dgisselq	2423d 19h	/wbuart32/trunk/bench/verilog/linetest.v
15	Added a set of lite-UARTs that only handle 8N1 to the repository.	dgisselq	2656d 03h	/wbuart32/trunk/bench/verilog/linetest.v
13	Adjusted documentation of OPT_STANDALONE, and updated internal README files.	dgisselq	2692d 01h	/wbuart32/trunk/bench/verilog/linetest.v
10	Adjusted for the new hardware flow control capability.	dgisselq	2692d 01h	/wbuart32/trunk/bench/verilog/linetest.v
5	Created independent peripheral, several toplevel tests, and updated documentation to match.	dgisselq	2736d 17h	/wbuart32/trunk/bench/verilog/linetest.v
2	A first version to be checked in. The rxuart.v and txuart.v files have been well tested elsewhere, although the test setup here has not been as well tested. Still, type 'make test' in the base directory and you will get an assurance that the entire thing works--if you would like.	dgisselq	2870d 02h	/wbuart32/trunk/bench/verilog/linetest.v